Cache modules are high-speed memories that facilitate fast retrieval of data. Typically, cache modules are relatively expensive and are characterized by a small size, especially in comparison to external memories.
The performance of modern processors based systems usually depend upon the cache module performances and especially to a relationship between cache hits and cache misses. A cache hit occurs when a data that is present in a cache module memory is requested. A cache miss occurs when the requested data is not present in the cache module and has to be fetched from another (usually external) memory.
Various cache module modules and processor architectures, as well as data retrieval schemes, were developed over the years, to meet increasing performance demands. These architectures included multi-port cache modules, multi-level cache module architecture, super scalar type processors and the like.
The following U.S patents and patent applications, all being incorporated herein by reference, provide a brief summary of some state of the art cache modules and data fetch methods: U.S. Pat. No. 4,853,846 of Johnson et al., titled “Bus expander with logic for virtualizing single cache control into dual channels with separate directories and prefetch for different processors”; U.S. patent application Ser. No. 20020069326 of Richardson et al., titled “Pipelines non-blocking level two cache system with inherent transaction collision-voidance”; U.S. Pat. No. 5,742,790 of Kawasaki titled “Detection circuit for identical and simultaneous access in a parallel processor system with a multi-way multi-port cache”; U.S. Pat. No. 6,081,873 of Hetherington et al., titled “In-line bank conflict detection and resolution in a multi-ported non-blocking cache”; and U.S. Pat. No. 6,272,597 of Fu et al., titled “Dual-ported, pipelined, two level cache system”.
Typically, a processor that requests data from a cache module is stalled or halted until it receives the requested data. When multiple cache miss events occur simultaneously the requesting processor can be halted for a prolonged time period, due to the latency associated with multiple fetch operations.
There is a need to provide a system and method that can handle in an efficient manner multiple cache miss events.